ANNOUNCE: MyHDL 0.1

[Jan Decaluwe]

I am happy to announce the initial public release of MyHDL, a
Python package for using Python as a hardware description language.

This may be of interest to:
- Pythoneers interested in applications of Python generators
- hardware designers interested in the wonders of Python

You can find it at http://jandecaluwe.com/Tools/MyHDL/Overview.html.

Release notes:

MyHDL 0.1
---------

MyHDL is a Python package for using Python as a hardware description
language. Popular hardware description languages, like Verilog and
VHDL, are compiled languages. MyHDL with Python can be viewed as a
"scripting language" counterpart of such languages. However, Python is
more accurately described as a very high level language (VHLL). MyHDL
users have access to the amazing power and elegance of Python for their
modeling work.

The key idea behind MyHDL is to use Python generators to model the
concurrency required in hardware descriptions. As generators are a
recent Python feature, MyHDL requires Python 2.2.2 or higher.

MyHDL 0.1 is the initial public release of the package. It can be used
to experiment with high level modeling, and with verification
techniques such as unit testing. But the primary goal is to generate
interest and to solicit feedback.

In a future release, MyHDL will hopefully be coupled to hardware
simulators for languages such as Verilog and VHDL. That would turn
Python into a powerful hardware verification language.

--
Jan Decaluwe - Resources bvba
Losbergenlaan 16, B-3010 Leuven, Belgium
mailto:jan@jandecaluwe.com
http://jandecaluwe.com