[ANNOUNCE] MyHDL 0.6 released
jan at jandecaluwe.com
Fri Jan 9 17:32:40 CET 2009
I'm happy to announce the release of MyHDL 0.6.
MyHDL is a Python package for using Python as a hardware
The highlight of this release is conversion to VHDL, in
addition to the existing Verilog capability. Furthermore,
the convertible subset has been broadened substantially
beyond synthesizable logic, to support test bench conversion.
For a complete overview, see:
To check whether MyHDL can be useful to you, please read:
To find out the details of what's new in this release:
You can download the release from SourceForge:
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a hardware description language:
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