ANN: Confluence -> Python for Hardware Verification

[Christopher Saunter]

Tom Hawkins (tom1 at launchbird.com) wrote:
: Over the weekend we released Confluence 0.4.6: the first
: version to included the new Python model generator.

Neato.  I have found Python to be very well suited to removing some of the 
pain of HDLs ;-)  - can you say how long the free trial licences of 
Confluence are likely to last for?

ta
cds


: Confluence is a functional programming language for hardware
: and logic design.  Though its syntax is much simpler than
: either Verilog or VHDL, it's semantics enables a level of
: design flexibility beyond the reach of either HDL.

: Til now, Confluence compiled into Verilog and VHDL for
: logic synthesis and cycle-accurate C for high-speed simulation
: and hardware-software co-development.

: With the addition of the Python model generator, hardware
: designers can now use the high-level constructs of our
: favorite language (Python!) to perform functional verification.

: We were very surprised by Python's simulation performance;
: Python simulation of our benchmarks was right on par with
: HDL event-based simulators.  Not bad for a "scripting" language!

: For more info on Confluence:

:   http://www.launchbird.com/

: To see Confluence output, including generated Python models
: visit any of the Confluence projects at:

:   http://www.opencores.org/

: Regards,
: Tom

: --
: Tom Hawkins
: Launchbird Design Systems, Inc.
: 952-200-3790
: tom1 at launchbird.com
: http://www.launchbird.com/