ANNOUNCE: MyHDL 0.1

[Thomas Heller]

Jan Decaluwe <jan at jandecaluwe.com> writes:

> Thomas Heller wrote:
> > What will be the future of this package?  
> 
> I will be actively promoting/developing it in the short term, but
> in the longer term this will depend on the amount of user interest.
> A good sign would be if people start complaining about performance,
> because that would mean they are actually using it <wink>.

So let me complain that I cannot print the PDF documentation, although
I'm not sure whether this is your fault or that of our printer ;-)

>  (The bad
> news would be that someone, perhaps me, would then have to recode 
> the package as an extension module in C.)
> 

I may be able to help with that (if it's really required).

> First on my list is to couple the package to a HDL simulator. My
> goal is to be able to use Python's unit test framework on hardware
> design written in an HDL - I believe Python would make a superior HVL.
> Unfortunately, I don't have access to any commercial simulator right
> now - only Icarus Verilog and I'm not sure that it supports the
> Verilog PLI completely. I'm also not yet clear on how to do it best -
> probably the best is to run MyHDL code in slave mode without
> time queue (delta cycles only).

I don't know *anything* about Icarus Verilog, but isn't there a limited
version of ModelSim in Xilinx Webpack?

> 
> >Ideas I have for it include
> > generation of VCD files to view the simulation results in graphical
> > mode, 
> 
> Definitely possible and interesting of course, but don't count on me for 
> that one. 
> 
> >and (eventually) generating VHDL code.
> 
> Well anticipated - it should indeed possible to generate HDL code from
> an elaborated MyHDL description - this could be interesting for the 
> synthesizable subset for example. I guess I would tackle Verilog
> first - as a back-end format it is just fine <wink>.

I don' care whether this is VDHL, Verilog or whatever, as long as
I can synthesize my hardware from it.
Maybe I'm missing the big picture, but what would you do with
a verified hardware description in Python (except to build the hardware
from it?)

I hope you get enough interested users so that this project starts
flying, I'm quite convinced there is enough potential in the combination
of hardware descriptions/simulations and Python (although I always was
quite disappointed that I didn't find anything of interest when googling
for 'Python HDL'.

Thanks,

Thomas