ANNOUNCE: MyHDL 0.1
jan at jandecaluwe.com
Tue Mar 11 10:38:11 CET 2003
Thomas Heller wrote:
> Jan Decaluwe <jan at jandecaluwe.com> writes:
> > I am happy to announce the initial public release of MyHDL, a Python
> > package for using Python as a hardware description language.
> > This may be of interest to:
> > - Pythoneers interested in applications of Python generators
> > - hardware designers interested in the wonders of Python
> Or Python programmers also doing VHDL from time to time...
> What will be the future of this package?
I will be actively promoting/developing it in the short term, but
in the longer term this will depend on the amount of user interest.
A good sign would be if people start complaining about performance,
because that would mean they are actually using it <wink>. (The bad
news would be that someone, perhaps me, would then have to recode
the package as an extension module in C.)
First on my list is to couple the package to a HDL simulator. My
goal is to be able to use Python's unit test framework on hardware
design written in an HDL - I believe Python would make a superior HVL.
Unfortunately, I don't have access to any commercial simulator right
now - only Icarus Verilog and I'm not sure that it supports the
Verilog PLI completely. I'm also not yet clear on how to do it best -
probably the best is to run MyHDL code in slave mode without
time queue (delta cycles only).
>Ideas I have for it include
> generation of VCD files to view the simulation results in graphical
Definitely possible and interesting of course, but don't count on me for
>and (eventually) generating VHDL code.
Well anticipated - it should indeed possible to generate HDL code from
an elaborated MyHDL description - this could be interesting for the
synthesizable subset for example. I guess I would tackle Verilog
first - as a back-end format it is just fine <wink>.
Jan Decaluwe - Resources bvba
Losbergenlaan 16, B-3010 Leuven, Belgium
mailto:jan at jandecaluwe.com
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