Thomas Heller theller at
Thu Feb 5 19:00:48 CET 2004

Jan Decaluwe <jan at> writes:

> I am happy to announce the release of MyHDL 0.4.  MyHDL is a Python
> package for using Python as a hardware description & verification
> language.
> MyHDL 0.4 supports the automatic conversion of a subset of MyHDL code
> to synthesizable Verilog code.

Very cool, but do you intend to add VHDL generation at some time?

Although it seems it would be better I had learned verilog instead.


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