Jan Decaluwe jan at
Thu Feb 5 18:14:59 CET 2004

I am happy to announce the release of MyHDL 0.4.  MyHDL is a Python
package for using Python as a hardware description & verification

MyHDL 0.4 supports the automatic conversion of a subset of MyHDL code
to synthesizable Verilog code. This feature provides a direct path
from Python to an FPGA or ASIC implementation.

For the details on the release, go here:

For a general overview and starting point, go here:

Regards, Jan

Jan Decaluwe - Resources bvba -
Losbergenlaan 16, B-3010 Leuven, Belgium
    Python is fun, and now you can design hardware with it:

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