ANNOUNCE: MyHDL 0.4
jan at jandecaluwe.com
Thu Feb 5 23:02:12 CET 2004
Thomas Heller wrote:
> Jan Decaluwe <jan at jandecaluwe.com> writes:
>>I am happy to announce the release of MyHDL 0.4. MyHDL is a Python
>>package for using Python as a hardware description & verification
>>MyHDL 0.4 supports the automatic conversion of a subset of MyHDL code
>>to synthesizable Verilog code.
> Very cool, but do you intend to add VHDL generation at some time?
> Although it seems it would be better I had learned verilog instead.
Verilog is quite allright as a back-end format :-)
VHDL output - no plans, for the following reasons:
1. I would need an open-source VHDL simulator *with PLI support*
An Icarus for VHDL, let's say (thanks, Stephen Williams!). To verify
output conversion, it is essential to have co-simulation. As far
as I know, this is just not there for VHDL.
2. The fact that Verilog co-simulation and conversion works,
demonstrates that "it can be done". There *is* now a path to
implementation using an intermediate :-) format that any
EDA tool will understand. For me personally and for
the myhdl technology it makes more sense to tackle other areas
(especially verification) than "to do it again". That having
said, I welcome any effort and any help from others to
fill in missing functionality, such as VHDL support.
Of course, I'll take back all of these points if sponsors show up.
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
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