Unification of Methods and Functions

[Greg Ewing]

David MacQuigg wrote:
> There is an analogy in the netlisting programs used in circuit design.
> Netlisting a big design is a time-consuming operation, so each cell is
> netlisted when it is saved.  When the design is simulated, there is a
> quick check of the time-stamps on the entire hierarchy, to make sure
> all of the incremental netlists are up-to-date.

This is a form of cacheing, which is a well-proven technique.
But it's an optimisation, and as such it should be the last
thing added to a design, and then only when it becomes necessary.

Also, there's a difference between cacheing and maintaining
redundant data representations. With a cache, if in doubt you
can always throw away the cache and re-calculate. But if your
design relies on incrementally keeping parallel data structures
up to date, if anything gets out of whack, you're hosed,
because you don't have the ability to re-calculate the
redundant data from scratch.

-- 
Greg Ewing, Computer Science Dept,
University of Canterbury,	
Christchurch, New Zealand
http://www.cosc.canterbury.ac.nz/~greg