[ANNOUNCE] MyHDL 0.5 released

Jan Decaluwe jan at jandecaluwe.com
Fri Jan 20 12:04:45 CET 2006


Michael wrote:
> Jan Decaluwe wrote:
> 
> 
>>I'm pleased to announce the release of MyHDL 0.5.
>>
>>MyHDL is an open-source package for using Python as a hardware
>>description and verification language. Moreover, it can convert
>>a design to Verilog. Thus, MyHDL provides a complete path
>>from Python to silicon.
> 
> 
> Jan,
> 
> 
> I'm not sure if you read c.l.p, but if you do...
> 
> I'm looking at the website and I see that you've now got an example showing
> translation to verilog - which is really cool. I also saw that someone's
> done what I view as a complex example - specifically the MU0 example [*]
> (which is a tutorial I remember from student days!) as a MyHDL simulation.
> 
>    * http://article.gmane.org/gmane.comp.python.myhdl/19/match=mu0
> 
> One question I've got, mainly because it strikes me as very intriguing is
> do you know if the MU0 processor as described is synthesisable or have a
> feeling as to how much work would be needed for it to be synthesisable?

This is a fairly "old" project (2003). At that time, MyHDL didn't
yet have conversion to Verilog.

After reviewing the code again, it's clear that it's written in
RTL (register-transfer level) style. This means that the building
blocks are combinatorial, or triggered on clock edges, closely
reflecting an actual implementation. As it is, it's not
convertible to Verilog (see the MyHDL manual for conversion
constraints), but it's close.

To someone with some synthesis experience, it should be fairly
straightforward to make the code synthesizable. I don't expect
that this would make the code more verbose or less clear.

> I've been watching your project grow over the past couple of years with
> great interest though little actual need at the moment, but for me seeing
> MU0 crop up piques my interest because that shows that MyHDL is getting up
> to a very interesting level.

As your interest was apparently triggered by an example, this
tells me that I should put more emphasis on publishing practical
examples, as conversion to Verilog was already introduced some time
ago (beginning of 2004).

Note also that by now, there are designers that use MyHDL in real
projects, showing that you really can use it to go from Python to
an FPGA (or ASIC). Moreover, with development tools such
as Xilinx WebPack (now on Linux also) that start from Verilog,
this can be done using a zero-cost development environment.

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com



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