SAGE for FPGA development
Blubaugh, David A.
dblubaugh at belcan.com
Thu Feb 14 17:35:25 CET 2008
Bill,
The potential idea that I had in store for SAGE would be to first be
able to develop complicated algorithms onto hardware. What I mean by
this is to take for example, a FFT and then be able to map the entire
algorithm into hardware, in a reasonable amount of time. It currently
takes a few months to develop floating or fixed-point algorithms onto
hardware. The idea behind this is that an algorithm would no longer be
limited by a von-Neumann based architecture, which means that the
algorithm could theoretically process data as fast as the material
science of semiconductors will allow. That would be the ultimate goal.
I believe SAGE is more than capable to turn this into a reality, will
the inclusion of MyHDL. Are you interested in being apart of this
development??
Thanks,
David Blubaugh
-----Original Message-----
From: Bill Hart [mailto:goodwillhart at googlemail.com]
Sent: Wednesday, February 13, 2008 7:45 PM
To: Blubaugh, David A.
Cc: William Stein
Subject: Re: Fwd: SAGE for FPGA development
Hi David,
I guess I don't know much about programming for FPGA's, though I know a
few people who do.
>From what I can gather from the MyHDL website, the package allows one to
specify silicon using python (converting the python to verilog code).
That seems like a powerful tool for designing silicon, but I can't quite
see why one would put this in SAGE. Yes, one would then be able to
specify silicon circuits in SAGE, but that's not going to allow SAGE to
run on FPGA's.
To make it useful, one would then need to modify some of the underlying
packages in SAGE, such as GMP, so that they run through the FPGA.
Alternatively, one would need to program specific fundamental SAGE
functions using MyHDL, then modify the higher level SAGE functions to
call them if an FPGA was available.
So I guess my question is, if MyHDL were in SAGE, who would actually use
it to specify silicon and then use that silicon functionality to do
mathematics?
I note that you work for Belcan. Do you yourself have exertise in using
MyHDL? What would you be able to contribute? Do you have a particular
application in mind that you'd like to code for SAGE using an FPGA?
I note that the MyHDL package is LGPL, which is a good thing.
Regards,
Bill Hart.
On 13/02/2008, Blubaugh, David A. <dblubaugh at belcan.com> wrote:
> Bill,
>
> Please ignore the security message. The information on FPGAs is that
they are more than capable of handling large algorithms, such as the
multidimensional FFT. I was wondering as to what would be required in
order to combine MyHDL with Sage??? How would I go about this
combination becoming a reality??? Any help will be more than
appreciated.
>
>
> David
>
>
>
>
> -----Original Message-----
> From: Bill Hart [mailto:goodwillhart at googlemail.com]
> Sent: Monday, February 11, 2008 9:09 PM
> To: sage-devel
> Cc: Blubaugh, David A.
> Subject: Re: Fwd: SAGE for FPGA development
>
> Dear David Blubaugh,
>
> Unfortunately I already read your email before reading the security
> notice at the bottom. What should I do? ;-)
>
> But seriously, regarding FPGA's, I'm somewhat out-of-touch with what
restrictions are placed on algorithms for FPGA's these days by readily
available hardware. Do you have some up-to-date information on this?
>
> Perhaps supporting FPGA's should be the domain of something like GMP
and other underlying numerical packages (or the SAGE versions of such
packages). For example I can certainly imagine an FFT running on an FPGA
to multiply huge integers.
>
> Regards,
>
> Bill Hart.
>
>
>
> On 8 Feb, 01:20, "William Stein" <wst... at gmail.com> wrote:
> > ------- Forwarded message -------
> > From: "Blubaugh, David A." <dbluba... at belcan.com>
> > To: wst... at gmail.com
> >
> > Cc:
> > Subject: SAGE for FPGA development
> > Date: Thu, 07 Feb 2008 14:26:13 -0800
> >
> > Sir,
> >
> > I was wondering if it was possible to integrate MyHDL into SAGE???
> > This would hopefully allow for the development of a system that
> > could be utilized to develop numerical algorithms onto FPGAs.
> >
> > Thanks,
> >
> > David Blubaugh
> >
> > This e-mail transmission contains information that is confidential
and may be privileged. It is intended only for the addressee(s) named
above. If you receive this e-mail in error, please do not read, copy or
disseminate it in any manner. If you are not the intended recipient, any
disclosure, copying, distribution or use of the contents of this
information is prohibited. Please reply to the message immediately by
informing the sender that the message was misdirected. After replying,
please erase it from your computer system. Your assistance in correcting
this error is appreciated.
> >
> > --
> > William Stein
> > Associate Professor of Mathematics
> > University of Washingtonhttp://wstein.org
>
More information about the Python-list
mailing list