Parsing VHDL with python, where to start.
paddy3118 at googlemail.com
Tue Jul 29 23:33:25 CEST 2008
On Jul 21, 12:09 pm, Svenn Are Bjerkem <svenn.bjer... at googlemail.com>
> I am in the need to write an application for PyQt to visualise the
> structure of a VHDL project I am working on. Looking for a sensible
> way to parse VHDL files and putting them into a data structure that
> PyQt can represent as a tree (or whatever the MVC is supporting)
> through search engines does not give me many hints. From what I know,
> VHDL is not a very easy language to parse. There seems to be a parser
> for perl available, but I do not know if it is wise to use a perl
> module as a template for writing something similar in python.
> My initial idea is to start simple and extend features in my
> application, but I fear that I may start off with wrong ideas how to
> parse and then code myself into a dead-end requiring myself to rewrite
> the whole application in order to get any further. I would start
> finding definitions of entities and the instantiations of these and
> build a tree from a set of external vhdl files stored in a file
> hierarchy. If somebody have a starting point where to get going with a
> task like this, I would be happy to know.
> kind regards,
Been their, partially done that.
I started parsing an old version of VHDL (VHDL 87 I think); using
regular expressions and carrying state around myself. It was tough,
and I was doing it , but then Work mentioned that they were going to
need to parse later versions of VHDL and that was a whole new ball-
game, specifically configuration type information could be mixed in
with the architecture. Luckily work had also decided to by in a
I learned that add-hoc parsers have limits to their maintainability
and become complex. You might not have such problems if your VHDL is
all in one library.
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