Parsing VHDL with python, where to start.

[c d saunter]

Svenn Are Bjerkem (svenn.bjerkem at googlemail.com) wrote:
: Hi,
: I am in the need to write an application for PyQt to visualise the
: structure of a VHDL project I am working on. Looking for a sensible
: way to parse VHDL files and putting them into a data structure that
: PyQt can represent as a tree (or whatever the MVC is supporting)
: through search engines does not give me many hints. From what I know,
: VHDL is not a very easy language to parse. There seems to be a parser
: for perl available, but I do not know if it is wise to use a perl
: module as a template for writing something similar in python.

Hi Sven,

How much of VHDL are you looking to parse?  Are you just looking at files 
intended for synthesis, or at simulation/testbench files as well?

I wrote a basic parser a few years ago for automatically stringing modules 
together, but it was very limited in scope.  I thought VHDL was quite 
simple to parse, it's very rigid.  Having written a basic one I realised 
I'd coded myself into a dead-end as you say.  Maybe not so simple after 
all... :-)

If I started again I'd use pyparsing:
http://pyparsing.wikispaces.com/

Looks like someone is already there in part:
http://pyparsing.wikispaces.com/message/view/home/103973

Regards,
Chris

: My initial idea is to start simple and extend features in my
: application, but I fear that I may start off with wrong ideas how to
: parse and then code myself into a dead-end requiring myself to rewrite
: the whole application in order to get any further. I would start
: finding definitions of entities and the instantiations of these and
: build a tree from a set of external vhdl files stored in a file
: hierarchy. If somebody have a starting point where to get going with a
: task like this, I would be happy to know.

: --
: kind regards,
: Svenn