correct way to catch exception with Python 'with' statement

Grant Edwards grant.b.edwards at
Fri Dec 2 14:51:17 EST 2016

On 2016-12-02, Marko Rauhamaa <marko at> wrote:
> Grant Edwards <grant.b.edwards at>:
>> In general CISC processors like x86, AMD64, 68K have read-modify-write
>> instructions that allow you to increment a memory location or
>> set/clear a bit in memory with a single instruction:
>>     INC.W  [R0]    # increment memory word whose addr is in register R0
> The x86 instruction set has a special lock prefix for the purpose:
>    <URL:>

The x86 already has single-instruction read-modify-write instruction,
so there's no possibility of your task being interrupted/suspended
during those single-instruction operations (which was sort of the
original topic).  What the lock prefix does is lock the _bus_ for the
duration of that one instruction so that other bus masters (other CPU
cores or DMA masters) can't access the memory bus in the middle of the
R-M-W instruction.  Obiously, if you've got multiple bus masters,
merely locking the CPU and not the bus may not be sufficient to avoid
race conditions.  Locking the CPU only prevents races between
different execution contexts (processes, threads, interrupt handlers)
on that one CPU.  If you've only got one CPU, and you know that none
of the DMA masters are going to write to your memory location, then
you don't need to lock the bus as long as your operation is a single

Grant Edwards               grant.b.edwards        Yow! Here I am at the flea
                                  at               market but nobody is buying
                                my urine sample bottles ...

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