verilog like class w/ bitslicing & int/long classtype

[MRAB]

John Machin wrote:
> On Jan 30, 9:02 am, mark.sea... at gmail.com wrote:
>> I'm trying to make a script environment with datatypes (or classes)
>> for accessing hardware registers.  At the top level, I would like the
>> ability to bitwise ops if bit slice brackets are used, but if no
>> brackets are used, I would like it to write/read the whole value.
>>
>> For example, if I have something like:
>>
>>>>> shadow_register = MyRegClass(0xAA)
>>>>> shadow_register
>> 170
>>>>> shadow_register[7:4] = 3  # <== changes value to 0x3A
>>>>> shadow_register
>> 58
>>>>> shadow_register = 0x89
>>>>> shadow_register
>> 137
>>>>> shadow_register[4:1]
>> 4
>>
>> I have the bitslice part working.  But of course as expected, if I
>> type>>> shadow_register
>>
>> <__main__.boo object at 0x00A130D0>
> 
> def __str__(self):
>     return "d" % self.value
> 
That should be:

     return "%d" % self.value